The present invention relates in general to oscillator circuits and, more particularly, to a differential oscillator having a controllable zero-crossing level of the differential output signal.
Oscillator circuits are commonly used in electronic circuit design to generate an oscillating output signal. In a ring oscillator for example, an odd number of inverters are serially coupled input-to-output with the output of the last stage coupled back to the input of the first stage. Many applications require a 50% duty cycle for the oscillating output signal. For example, an oscillator may need to generate a symmetrical clock signal if the external logic clocks off both the rising and falling edges of the clock signal. The conventional ring oscillator has problems generating a symmetrical waveform because of delay differences through the inverter stages. The duty cycle of the oscillating signal may be off by as much as .+-.10% which is unacceptable in many applications.
A common solution to the problem of maintaining a 50% duty cycle is to design an oscillator to run at twice the desired frequency and then divide down the oscillating signal, for example through a D-type flipflop configured as a divide-by-two counter, to generate the 50% duty cycle waveform operating at the desired frequency. One problem with this solution is the need to operate the oscillator at twice the desired frequency. Since oscillators have an inherent upper frequency limit, dependent on materials and processing, such a solution limits the useable bandwidth of the oscillator by one-half.
Therefore, a need exists for an improved oscillator circuit generating a high frequency oscillating symmetrical waveform with a 50% duty cycle.